Known dynamic random access memories (DRAMs) that use a common N-channel metal oxide semiconductor (N-channel MOS) field effect transistor (FET) as a cell transistor of the memory cell have the problem of high current consumption of a word line circuit that drives word lines connected to the gates of the cell transistors of the memory cells.
Specifically, high-level values are written to the memory cells of such memories by applying a high-level voltage to bit lines (data lines) connected to the sources of the memory cells. Therefore, the high-level voltage (high voltage Vpp) of the word lines connected to the gates of the memory cells must be higher than the high-level voltage of the bit lines by at least the threshold voltage Vt of the cell transistors. Furthermore, in a state in which data is stored in the memory cells with the voltage of the word lines held at a low level, the threshold voltage Vt must be significantly high to keep the leak current between the drain and the source of each cell transistor below the order of f (femto: 1×1015) A (ampere). Furthermore, when the bit lines are at a high level, the voltage of the word lines (the gate voltage of the cell transistors) sufficient to write the full high-level value of the bit lines to the memory cells at high speed is considerably as high as 3.0 V or more, because this is a source follower (grounded drain) operation in a state in which the substrate is biased at the voltage Vt. The high-level voltage Vpp of the word lines has recently been decreased to about 2.6 V to 2.8 V because of the necessity for decreasing the word line voltage as DRAMs become finer. Therefore, the threshold voltage Vt of cell transistors must also be decreased. However, the decrease in threshold voltage Vt increases the leak current of memory cells. To prevent it, negative voltages from −0.2 V to −0.5 V are used as the low-level voltage (low voltage Vnn) of word lines. These high-level voltages from 2.6 V to 2.8 V of word lines and negative low-level voltages from −0.2 V to −0.5 V of word lines are generated from the internal voltage of DRAMs by the charge pump circuits in DRAM chips (referred to as a Vpp pump and a Vnn pump, respectively). Since such negative voltages are used as the low-level voltage of word lines, the high-level voltage is decreased to 2.6 V to 2.8 V. However, the internal voltage for generating it is also decreased to about 1.6 V, so that their voltage ratio remains large, and the current consumption is also high because of conversion loss due to the low efficiency of the charge pump circuits, to be described below.
According to S. I. Cho, “IEEE Journal of Solid State Circuits”, pp. 1726-1729, vol. 38, no. 10, October 2003, general charge pump circuits are inefficient; particularly, the efficiency of Vpp pumps for generating a high voltage is as low as about 40%. Furthermore, according to Y. Nakagome, “IEEE Journal of Solid State Circuits”, pp. 465-472, vol. 26, no. 4, April 1991, the low efficiency of charge pump circuits is caused by large current flowing through control and driving circuits because a single kind of transistors are used to prevent reverse bias of the junctions. In other words, the Vpp pump is formed of N-channel MOS FETs. Accordingly, in order to control a high voltage, a higher voltage must be applied. To generate this voltage, a pump using a capacitor is needed; for example, to generate the high-level voltage Vpp twice as high as a supply voltage, the maximum three times the supply voltage must be generated by the control circuit, which causes high current consumption.
A current of a value calculated by multiplying the current actually used in the circuit (word line circuit) of the memory by the reciprocal of efficiency expressed in percentages flows from the power supply. Accordingly, with an efficiency of 40%, a current 2.5 times as high as current used in an actual word line circuit is consumed in its memory chip. A recent increase in memory capacity of DRAMs has increased word lines that must be activated at once. In addition, particularly in synchronous dynamic random access memories (SDRAMs), all the banks are refreshed at the same time. This needs to activate word lines of a bank-number multiple (normally, four banks) of that of normal access, resulting in current consumption as high as 20 mA for 512-Mbit SDRAMs. This has become a significant obstacle to reduction in normal access current or refresh current.
On the other hand, a known example of a method not using such a charge pump circuit for generating a voltage Vpp higher than the internal voltage is one using a booster circuit. The booster circuit is a circuit for boosting voltage using a capacitor and a switch using an N-channel MOS FET, which has a well-known structure used when DRAMs are not made of complementary metal oxide semiconductor (CMOS) currently used but are made of only N-type MOS (until the middle of 1980s when DRAMs earlier than 1-Mbit DRAMs are used).
Japanese Unexamined Patent Application Publication No. 6-139776 discloses an idea about enhancing the speed of this booster circuit. That is to say, there are various additional parasitic capacitors around a row address decoder. The booster circuit must boost the nodes connected to those capacitors. Accordingly, if the capacitors have large capacitance, it takes much time to boost them, precluding high-speed operation. To solve this problem, the voltage to be applied to those nodes is raised to a predetermined level in advance through another route via a switch, and then the predetermined-level voltage is raised to a word-line voltage level higher than that using the booster circuit, without relying on the booster circuit for all the boosting, thereby reducing the total time to boost the voltage to the nodes.
However, this method only achieves high-speed boosting of the voltage but does not achieve reduction of current consumption. Furthermore, recent general memory systems supply high DC voltage generated from supply voltage to word lines using a charge pump circuit, as described above. With such a structure, there is considered no method for achieving high speed and low current consumption in supplying a high voltage.